Karnaugh Map (K-Map) Solver & Boolean Logic Simplifier

A Karnaugh map (K-Map) solver is a digital logic simplification tool used to reduce complex Boolean algebra expressions and truth tables into minimal two-level logic forms. Introduced by Maurice Karnaugh in 1953 as a refinement of Edward Veitch's chart, a Karnaugh map arranges truth-table combinations in a two-dimensional grid where adjacent cells differ by only a single bit.

In digital electronics, computer architecture, and discrete mathematics courses, minimizing a Boolean function reduces the number of logic gates and gate inputs (literals) required to build a combinational circuit. Fewer gates generally mean lower propagation delay, smaller silicon area, and simpler breadboard or FPGA wiring.

This online K-Map studio combines visual loop grouping with an exact Quine–McCluskey and minimum-cost cover engine. Instead of showing only a final equation, it illustrates how each prime implicant group is formed on the Gray-coded grid, which input variables change state inside the loop, and why those variables cancel out algebraically.

Karnaugh maps rely on the algebraic identity AB + AB' = A(B + B') = A(1) = A. Whenever two minterms share every variable except one—which appears uncomplemented in one cell and complemented in the other—that changing variable can be eliminated.

To make single-bit differences visually adjacent, K-Map row and column headers are ordered in Gray code (00, 01, 11, 10) rather than standard binary order (00, 01, 10, 11). Because of this ordering, any two cells that share a horizontal or vertical edge—including cells on opposite outer edges that wrap around like a torus—differ by exactly one variable:

• Singleton (1 cell): Covers 20 = 1 cell. Eliminates 0 variables and retains all n literals.
• Pair (2 cells): Covers 21 = 2 adjacent cells. Eliminates 1 variable that changes between 0 and 1.
• Quad (4 cells): Covers 22 = 4 adjacent cells in a 1×4, 4×1, or 2×2 rectangle (including the four outer corners of a 4-variable map). Eliminates 2 variables.
• Octet (8 cells): Covers 23 = 8 adjacent cells. Eliminates 3 variables.
• Hexadecad (16 cells): Covers 24 = 16 cells, eliminating 4 variables (reducing a 4-variable map to a constant 1 in SOP or 0 in POS).

When you click or hover over any prime implicant badge in the studio, the corresponding cells on the K-Map and rows in the truth table highlight together, showing outer loop borders and wrap-around edges clearly.

Combinational logic circuits are commonly expressed in one of two canonical or minimal two-level forms, both of which are computed simultaneously by this solver:

• Sum of Products (SOP / Minterm Mode): Targets truth-table rows where the output is 1 (minterms, denoted Σm). Each group forms an AND product term where a 1 bit represents an uncomplemented variable (A) and a 0 bit represents a complemented variable (A'). All product terms are combined with an OR gate (AND-OR or two-level NAND-NAND logic).
• Product of Sums (POS / Maxterm Mode): Targets truth-table rows where the output is 0 (maxterms, denoted ΠM). Each group of 0s forms an OR sum clause where a 0 bit represents an uncomplemented variable (A) and a 1 bit represents a complemented variable (A'). All sum clauses are multiplied with an AND gate (OR-AND or two-level NOR-NOR logic).

In many real-world digital systems—such as a BCD to 7-segment display decoder where binary inputs 1010 through 1111 (decimal 10–15) never occur in valid Binary-Coded Decimal—certain input combinations are Don't-Care conditions (X). The solver automatically treats each X cell as 1 (in SOP) or 0 (in POS) only when doing so enlarges a prime implicant loop and reduces literals; otherwise, it leaves the Don't-Care cell uncovered so no extra gates are added.

You can switch the variable count between 2 and 5 variables at any time and customize variable identifiers (for example, A, B, C, D or W, X, Y, Z or sensor names like S1, S2, S3):

• 2-Variable K-Map (2×2 Grid, 4 Cells): Rows represent variable A (0, 1) and columns represent variable B (0, 1), covering minterms m0 through m3.
• 3-Variable K-Map (2×4 Grid, 8 Cells): Rows represent A (0, 1) and columns represent Gray-coded BC (00, 01, 11, 10), covering minterms m0 through m7. Left and right edges wrap around (for example, m0 is adjacent to m2, and m4 is adjacent to m6).
• 4-Variable K-Map (4×4 Grid, 16 Cells): Rows represent Gray-coded AB (00, 01, 11, 10) and columns represent Gray-coded CD (00, 01, 11, 10), covering m0 through m15. Top and bottom edges wrap, left and right edges wrap, and all four corners (m0, m2, m8, m10) form a valid 4-cell Quad.
• 5-Variable K-Map (Dual 4×4 Overlay Planes, 32 Cells): Rendered as two side-by-side 4×4 planes: Plane A = 0 (m0–m15) and Plane A = 1 (m16–m31). Cells in identical row and column positions across the two planes (such as m0 and m16, or m15 and m31) are adjacent in the 5th dimension and can combine into 3D groups that eliminate variable A.

While visual K-Map inspection works well on paper for 3 or 4 variables, it is easy to miss wrap-around groups or choose a non-minimal cover when several overlapping loops exist. Under the hood, this tool runs a complete Quine–McCluskey (tabular minimization) algorithm paired with an exact branch-and-bound minimum-literal cover solver.

Open the Prime Implicant Chart tab to inspect the tabular stages:

• k-Cube Combination Stages: Shows how individual binary minterms (0-cubes) are grouped by the number of 1 bits and iteratively combined into 1-cubes (pairs), 2-cubes (quads), 3-cubes (octets), and higher-order implicants by replacing single-bit differences with a dash (-).
• Essential Prime Implicants (EPIs): A prime implicant is marked Essential if it covers at least one required minterm (or maxterm) that no other prime implicant covers. Essential prime implicants must be included in every minimal solution.
• Minimum-Cost Cover Selection: When cyclic or overlapping non-essential prime implicants remain after EPIs are selected, the solver evaluates candidate covers to minimize the total number of product/sum terms first and the total literal count second.

A minimal Boolean expression is not always glitch-free in physical hardware. Because physical NOT, AND, and OR gates have non-zero propagation delays, when an input variable changes state (for example, transitioning between two adjacent minterms mi and mj that differ by 1 bit), one product term may turn OFF slightly before another product term turns ON.

If those two adjacent active cells are covered by separate, non-overlapping prime implicant loops rather than a single shared loop, the circuit can experience a momentary false output pulse known as a static-1 hazard (in SOP) or static-0 hazard (in POS).

The Static Hazards & Gates tab automatically scans all adjacent target pairs (Hamming distance 1) across the K-Map. If any adjacent pair lacks a shared selected loop, the tool flags the transition and identifies the redundant consensus prime implicant you can add to bridge the two loops and eliminate the timing glitch.

Homework problems, lab manuals, and hardware specifications describe logic functions in different ways. The studio keeps four input methods synchronized in real time so you can enter a problem in whichever format you have and immediately read the others:

• Interactive K-Map Grid & Paint Brush: Click cells directly to cycle through 0 → 1 → X, or select a dedicated Paint 1, Paint 0, or Paint X brush for rapid entry. Each cell displays its decimal minterm index (m0..m31) and Gray-code binary coordinates.
• Minterm & Don't-Care Lists: Enter comma-separated indices or ranges such as 0, 2, 5-7, 8, 10 and Don't-Care indices such as 10-15.
• Boolean Expression Parser: Type an unminimized or canonical algebraic expression using apostrophe notation (A'B + BC'), boolean operator symbols (!A & B | C, ~A * B, A ^ B), word operators (NOT A AND B OR C), or parenthesized POS expressions ((A + B)(C' + D)) to populate the truth table and K-Map automatically.
• Synchronized Truth Table: Toggle output values (0, 1, X) row by row in the binary truth table and see which prime implicants cover each minterm.

Once your K-Map is simplified, open the HDL / LaTeX Export tab to generate clean, copy-ready code for lab reports, simulation testbenches, or FPGA synthesis:

• Verilog HDL: Generates a synthesizable module kmap_logic with continuous assign F = ...; dataflow syntax using your custom input wire names.
• VHDL: Generates a complete IEEE STD_LOGIC_1164 entity and behavioral architecture assignment.
• Python Function: Generates a type-annotated Python function evaluate_kmap(...) for quick software verification or automated grading scripts.
• LaTeX Equation & Array: Generates a LaTeX equation block alongside an array environment representing the Gray-coded K-Map grid for direct inclusion in academic papers and lab write-ups.
• Truth Table CSV Download: Exports the complete binary truth table with custom variable columns, minterm labels, and output states as a .csv file.

All Boolean expression parsing, Quine–McCluskey prime implicant generation, hazard detection, and HDL code formatting execute locally in your browser using JavaScript. Your truth tables, expressions, and homework presets are processed immediately without round-trips to an external solver server.

If you are learning digital logic design for the first time, use the built-in Exam & Lab Presets bar at the top of the workspace to load classic examples—including the 4-Corners Wrap Quad, BCD 7-Segment Decoder (Segment a) with Don't Cares, 3-Bit Majority Voter, Consensus & Static Hazard Demo, POS Maxterm Grouping, and the 5-Variable Dual Plane map.

For additional student and developer utilities on AabiTech, explore our CGPA to Percentage Converter for academic grading scales, JSON Formatter for inspecting structured data, or Regex Tester for validating pattern expressions.